There continues to be a demand for a higher degree of integration for electronic devices that mount semiconductor devices. To meet such goals, there has been a corresponding demand for the reduction in the size of individual semiconductor device packages. One type of semiconductor device package that has been proposed is the “chip size package (CSP)”.
FIG. 12 shows a semiconductor device disclosed in U.S. Patent Application Publication 2001/00048116 A1. In this device, a metal plate is provided that is slightly larger than a semiconductor chip 101. The metal plate is processed to have a dish-like shape (e.g., a recessed portion) and the semiconductor chip 101 is mounted in a concave portion 111 of the metal plate (hereinafter referred to as metal base 110).
A semiconductor chip 101 in this example is a metal-oxide-semiconductor (MOS) transistor chip. A drain electrode (not shown) is formed on the rear surface of the semiconductor chip 101 and is fixed directly to the bottom surface of the concave portion 111. The space surrounding the semiconductor chip 101 in the concave portion 111 is filled with a resin 113 for sealing. A gate electrode 107 and a source electrode 108 are formed on the surface of the semiconductor chip 101 to be coplanar with the surface of the metal base 110. Regions within a peripheral portion 112 on the surface of the metal base 110 serve as drain connection electrodes 115.
The semiconductor device is mounted face down onto a mounting substrate (not shown in the drawing) so that drain connection electrodes 115 in peripheral portions 112 of metal base 110 are connected to drain connection electrode pad portion provided on the mounting substrate. At the same time, the gate electrode 107 and source electrode 108 are connected to a gate electrode pad portion and source electrode pad portion (also not shown in the drawing).
The above publication also proposes, as shown in FIG. 13(a), a structure in which a concave portion 121 is formed leaving portions 122 on both sides of a metal base 120. The surfaces of both side portions 122 are used as drain electrodes 125. In addition, as shown in FIG. 13(b), the publication shows a structure in which, instead of both side portions, one side portion 132 of a metal base 130 is left to form a concave portion 131. Grooves 133, as deep as the entire thickness of the metal base 130, are formed in several locations along the length of the one side portion 132. The surfaces of the regions separated by grooves 133 are used as drain electrodes 135.
A technique similar to the one shown in FIG. 13(a) is disclosed in Japanese publication 08-78657 A (the illustration of which is not included herein). In this technique, a concave portion is formed leaving both side portions. A semiconductor chip is mounted in the concave portion. The device is mounted face down, with the surfaces of both side portions being coplanar with electrodes on the surface of the semiconductor chip.
U.S. Pat. No. 6,133,634 discloses a semiconductor device that is almost identical to the semiconductor device shown in FIG. 14. In this semiconductor device, a metal base 140 receives press work, or the like, to form a concave portion 141 and leaving a peripheral portion 142. A semiconductor chip 101 is fixed in the concave portion 141. The surface of the peripheral portion 142 of the metal base 140 is substantially coplanar with electrodes 102 that are formed on the semiconductor chip 101. Solder balls 103 are formed on the surface of the peripheral portion 142 and on the electrodes 102 on the surface of the semiconductor chip 101. This device is mounted face down.
In the above conventional devices, the metal base is slightly larger in surface area than the semiconductor chip, and the total thickness is the sum of the thickness of the semiconductor device and the thickness of the metal base (at the bottom of a concave portion). Furthermore, there is no need to bond a metal wire, or the like, to the semiconductor device, and resin is not necessary for sealing the package. This makes it possible to reduce the size and thickness of a semiconductor device chip holding package. Further, such a relatively simple structure can be easy to manufacture. Another advantage can be heat dissipation. When such structures are mounted, the metal base can function as a heat sink, thereby dissipating heat.
However, inspections by the inventors of the present invention are believed to show latent problems inherent in the above structures. In a device in which a concave portion is formed that leaves a peripheral portion of a metal base, such as that of FIGS. 12 and 14, such a concave portion is obtained through press work or etching of the metal base. Finishing a device with such a relatively complicated process can make it difficult to form a desired shape with a high degree of precision. Thus, such metal base forming techniques present an obstacle to cost reduction. The semiconductor devices shown in FIG. 13(a) and 13(b) are superior in this regard (i.e., size and/or cost reduction), because both side portions (or one side portion) can be formed by bending or cutting. Thus, achieving higher processing precision can be relatively easy. Additionally, such approaches can have improved heat dissipation capabilities and improved mechanical strength, despite being smaller and/or thinner.
However, in a semiconductor device like that of FIG. 13(a), a drain connection electrode 125 has a larger area than the gate electrode 107 and source electrode 108, because the side portions 122 of metal base 120 have flat surfaces and the entirety of the flat surfaces are used to form the drain connection electrode 125. This means that when the device is mounted face down, the heat capacity of the drain connection electrode 125 is larger than that of the gate electrode 107 and source electrode 108. Therefore, it can be necessary to supply a larger amount of solder to drain connection electrodes 125 than the solder amount for gate electrode 107 and source electrode 108 when mounting the device to a mounting substrate with solder. As a result, the solder density on the mounting substrate can be uneven. Further, heat capacitance of the solder is irregular.
Accordingly, higher temperatures at the drain electrodes 125 can be necessary during a solder reflow step, and such a higher temperature can bring thermal damage to a part of the semiconductor device. In particular, damage may occur at a portion where the semiconductor chip is connected to the metal base. Further, such higher temperatures can reduce the reliability of a connection to gate electrode 107 and source electrode 108 when the solder amount is low. This can ultimately lower the reliability of the mounting.
Another drawback to an approach like that of FIG. 13(a) can be the substantially coplanar arrangement of the drain connection electrodes 125 with the surfaces of the gate electrode 107 and the source electrode 108. When the semiconductor device is mounted face down onto the mounting substrate, the gate electrode 107 and source electrode 108 can collide against the surface of the mounting substrate, and cause mechanical damage to such electrodes and/or to other parts of the semiconductor chip 101.
It is noted that the semiconductor devices like those shown in FIGS. 12 and 14 can be subject to the same above drawbacks, as the drain connection electrodes for such structures like that of FIG. 13(a).
Similarly, the semiconductor device shown in FIG. 13(b) includes a drain connection electrode 135 having a larger area than a gate electrode or source electrode. The device thus suffers from similar problems, including varying solder amounts, arising from variances in heat capacity, accompanying thermal damage, and lowered reliability in a solder connection.
If drain connection electrodes 135 are reduced in area, heat capacity of the individual drain connection electrodes during a mounting process can be reduced, and can address the above drawbacks. However, drain connection electrodes 135 are in regions separated by grooves 133 as deep as the entire metal base 130. Thus, in order to separate drain connection electrodes 135, each of the drain connection electrodes 135 would be cantilevered with respect to the metal base 130. This can lower the mechanical strength of the drain connection electrodes 135 and weakens the metal base supporting strength when the device is mounted on the mounting substrate. Thus, such a modification can present another factor to lower the mounting reliability.
Still further, like the device of FIG. 13(a), in the device of FIG. 13(b) drain connection electrodes 135 can have a surface essentially level with that of the gate electrode 107 and source electrode 108. Thus, an approach like that of FIG. 13(b) can also suffer from mechanical damage when mounting takes place.
In light of the above, it would be desirable to arrive at a semiconductor device having an improved mounting reliability with respect to conventional approaches. In particular, it would be desirable to arrive at such a result by improving soldering upon mounting such a device.